Common to most software development processes is that system functionalities are defined early
in the life cycle in terms of informal requirements and visual models. As requirement descriptions
evolve, they quickly become error-prone and difficult to understand leading to prolonged detrimental
effects on reliability, cost, and safety of a software system that are very costly to fix in later phases
of the software development process. Thus, the development of techniques and tools to support
requirement specification development, understanding, validation, verification, maintenance and reuse
becomes an important issue.
This thesis proposes a novel methodology named Early Stages V&V (Early Stages Validation &
Verification), which combines the semi-formal scenario-based Use Case Maps language with formal
techniques to help comprehend, validate and verify requirements. UCM models allow the description
of functional requirements and high-level designs at early stages of the development process. Use
Case Maps is being standardized as part of the User Requirements Notation (URN), the most recent
addition to ITU-T's family of languages. In the first part of the thesis, we propose a concise and
rigorous formal semantics for Use Case Maps based on Abstract State Machines (ASM) formalism.
The resulting semantics are embedded in an ASM-UCM simulation engine and are expressed in
AsmL, an advanced ASM-based executable specification language, which is used to validate UCM
models through simulation.
Timing issues are often overlooked during the initial system design and treated as separate
behavioral issues and therefore described in separate models. In the second part of the thesis,
we extend the Use Case Maps language to cover timing constraints. A potential timed version
of UCM (called Timed UCM) is formalized using Clocked Transition Systems (CTS) and Timed
Automata (TA). The proposed semantics can be applied to comprehend, analyze, validate and
verify (using model checking) timed UCM models. In addition, we have proposed a novel UCM-based
property pattern system that combines qualitative, real-time and architectural properties into
a single graphical representation. The resulting pattern system is mapped to popular temporal logics
CTL, TCTL and ArTCTL (Architectural real-time temporal logic), which is an extension to TCTL
introduced in this research that provides temporal logics with architectural scopes.
In order to achieve an efficient validation and verification of UCM models and to assess the
impact of a specification change (e.g. as a result of a bug fixing or a feature upgrade), we extend
the application of the well-known technique of program slicing to Use Case Maps language.
An ongoing example of a simple telephone system is used to illustrate these concepts. The thesis
validates the Early Stage V&V methodology by implementing it and applying it to two case studies:
IP Multicast Protocol and an Online Store application.
- 02 May 2008
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| Title || Formal Semantics and Verification of Use Case Maps |
| Authors || Jameleddine Hassine |
| Type || Thesis |
| Conference/Journal Title || |
| Volume/Number || |
| Editors || |
| Publisher || Concordia University, Canada |
| Month || April |
| Year || 2008 |
| Pages || 299 |
| Keywords || ArTCTL, ASM, CTS, Model Checking, Slicing, Timed Automata, Temporal Logic, UCM, Verification |