Abstract

The ability to perform quantitative analysis at the requirements level supports the detection of design errors during the early stages of a software development life cycle. This would help reduce the cost of later redesign activities in case of unsatisfactory performance. This paper presents a novel approach to perform schedulability analysis at the requirement stage using Timed Use Case Maps (TUCM) language. The proposed approach relies on the computation of Worst-Case Execution Time (WCET), resource allocation and scheduling policies. Timing and resource constraints are first incorporated into UCM specifications, then mapped to Abstract State Machines (ASM) formalism and implemented in Asm L? language, allowing for simulation and schedulability analysis. The applicability of the approach is illustrated using an example of the Automatic Protection Switching (APS) feature.

-- Daniel Amyot - 05 Nov 2009

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